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january 2012 i ? 2012 microsemi corporation act 2 family fpgas features ? up to 8,000 gate array gates (20,000 pld equivalent gates) ? replaces up to 200 ttl packages ? replaces up to eighty 20-pin pal ? packages ? design library with over 500 macro functions ? single-module sequence functions ? wide-input combinatorial functions ? up to 1,232 programmable logic modules ? up to 998 flip-flops ? datapath performance at 105 mhz ? 16-bit accumulator performance to 39 mhz ? two in-circuit diagnostic probe pins support speed analysis to 50 mhz ? two high-speed, low- skew clock networks ? i/o drive to 10 ma ? nonvolatile, user programmable ? logic fully tested prior to shipment ? 1.0 micron cmos technology table 1 ? act 2 product family profile device a1225a a1240a a1280a capacity gate array equivalent gates 2,500 4,000 8,000 pld equivalent gates 6,250 10,000 20,000 ttl equivalent package 63 100 200 20-pin pal equivalent packages 25 40 80 logic modules 451 684 1,232 s-module 231 348 624 c-module 220 336 608 flip-flops (maximum) 382 568 998 routing resources horizontal tracks/channel 36 36 36 vertical tracks/channel 15 15 15 plice antifuse elements 250,000 400,000 750,000 user i/os (maximum) 83 104 140 performance 1 16-bit prescaled counters 105 mhz 100 mhz 85 mhz 16-bit loadable counters 70 mhz 69 mhz 67 mhz 16-bit accumulators 39 mhz 38 mhz 36 mhz packages 2 cpga plcc pqfp vqfp tqfp cqfp pg100 pl84 pq100 vq100 ? ? pg132 pl84 pq144 ? tq176 ? pg176 pl84 pq160 ? tq176 cq172 notes: 1. performance is based on ?2 speed devices at commercial worst-case operating cond itions using prep benchmarks, suite #1, version 1.2, dated 3-28-93. any analysis is not endorsed by prep. 2. see the "product plan" on page iii for package availability. revision 8
act 2 family fpgas ii revision 8 ordering information _ part number speed grade package type package lead count c = commercial (0 to +70c) i = industrial (?40 to +85c) m = military (?55 to +125c) b = mil-std-883 application (t emperature range) pl = plastic j-leaded chip carrier pq = plastic quad flat pack cq = ceramic quad flat pack pg = ceramic pin grid array tq = thin (1.4 mm) quad flat pack vq = very thin (1.0 mm) quad flat pack blank = standard speed ?1 = approximately 15% faster than standard ?2 = approximately 25% faster than standard a1225 = 2,500 gates a1240 = 4,000 gates a1280 = 8,000 gates a1280 1 die revision a = 1.0 m cmos process a pg 176 g c lead-free packaging blank = standard packaging g = rohs compliant packaging
act 2 family fpgas revision 8 iii product plan device resources contact your local microsemi soc products gr oup representative for device availability: http://www.microsemi.com/soc/contact/default.aspx . device/package speed grade 1 application 1 std. ?1 ?2 c i m b a1225a device 84-pin plastic leaded chip carrier (pl) ?? ? ?? ?? 100-pin plastic quad flatpack (pq) ?? ? ?? ?? 100-pin very thin quad flatpack (vq) ?? ? ? ? ?? 100-pin ceramic pin grid array (pg) ?? ? ? ? ?? a1240a device 84-pin plastic leaded chip carrier (pl) ?? ? ?? ?? 132-pin ceramic pin grid array (pg) ?? ? ? ? ?? 144-pin plastic quad flat pack (pq) ?? ? ?? ?? 176-pin thin (1.4 mm) quad flat pack (tq) ?? ? ? ? ?? a1280a device 160-pin plastic quad flatpack (pq) ?? ? ?? ?? 172-pin ceramic quad flatpack (cq) ?? ? ? ? ?? 176-pin ceramic pin grid array (pg) ?? ? ? ? ?? 176-pin thin (1.4 mm) quad flat pack (tq) ?? ? ? ? ?? notes: 1. applications: c = commercial i = industrial m = military b = mil-std-883 availability: ? = available p = planned ? = not planned speed grade: ?1 = approx. 15% faster than std. ?2 = approx. 25% faster than std. 2. contact your microsemi soc products group sales representative for product availability. device series logic modules gates user i/os pg176 pg132 pg100 pq160 pq144 pq100 pl84 cq172 tq176 vq100 a1225a 451 2,500 ? ? 83 ? ? 83 72 ? ? 83 a1240a 684 4,000 ? 104 ? ? 104 ? 72 ? 104 ? a1280a 1,232 8,000 140 ? ? 125 ? ? 72 140 140 ?
act 2 family fpgas revision 8 iv table of contents act 2 family overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 detailed specifications operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 act 2 timing model 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 package pin assignments pl84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 pq100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 pq144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 pq160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 vq100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 cq172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 pg100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 pg132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 pg176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
revision 8 1-1 1 ? act 2 family overview general description the act 2 family represents actel?s second generation of field programmable gate arrays (fpgas). the act 2 family pres ents a two-module architecture, consisting of c-modules and s- modules. these modules are optimized for both comb inatorial and sequential designs. based on actel?s patented channeled array architecture, the act 2 family provides significant enhancements to gate density and performance while maintaining downward compatibility with the act 1 design environment and upward compatibility with the act 3 design environment. the devices are implemented in silicon gate, 1.0- m, two-level metal cmos, and employ actel?s plice? antifuse technology. this revolutionary architecture offers gate array design flexibility, hi gh performance, and fast time-to-production with user programming. the act 2 family is supported by the designer and designer advantage systems, which offers automatic pin assignment, va lidation of electrical and design rules, automatic placement and routing, timing analysis, user programming, an d diagnostic prob e capabilities. the systems are supported on the followi ng platforms: 386/486? pc, sun?, and hp? wor kstations. the systems provide cae interfaces to the following design environments: cadence, viewlogic ? , mentor graphics ? , and orcad?.

revision 8 2-1 2 ? detailed specifications operating conditions table 2-1 ? absolute maximum ratings 1 symbol parameter limits units vcc dc supply voltage ?0.5 to +7.0 v vi input voltage ?0.5 to vcc + 0.5 v vo output voltage ?0.5 to vcc + 0.5 v iio i/o source sink current 2 20 ma t stg storage temperature ?65 to +150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than vcc + 0.5 v for less than gnd ?0.5 v, the internal protection diodes will be forward biased and can draw excessive current. table 2-2 ? recommended operating conditions parameter commercial industrial military units temperature range* 0 to +70 ?40 to +85 ?55 to +125 c power supply tolerance 5 10 10 %vcc note: *ambient temperature (t a ) is used for commercial and indus trial; case temperature (t c ) is used for military.
detailed specifications 2-2 revision 8 table 2-3 ? electrical specifications symbol parameter commercial industrial military units min. max. min. max. min. max. voh 1 (ioh = ?10 ma) 2 2.4 ? ? ? ? ? v (ioh = ?6 ma) 3.84 ? ? ? ? ? v (ioh = ?4 ma) ? ? 3.7 ? 3.7 ? v vol 1 (iol = 10 ma) 2 ?0.5? ? ? ?v (iol = 6 ma) ? 0.33 ? 0.40 ? 0.40 v vil ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v vih 2.0 vcc + 0.3 2.0 vcc + 0.3 2.0 vcc + 0.3 v input transition time t r , t f 2 ? 500 ? 500 ? 500 ns c io i/o capacitance 2,3 ?10?10?10pf standby current, icc 4 (typical = 1 ma) ? 2 ? 10 ? 20 ma leakage current 5 ?10 +10 ?10 +10 ?10 +10 a icc(d) dynamic vcc supply current. see the power dissipation section. notes: 1. only one output tested at a time. vcc = minimum. 2. not tested, for information only. 3. includes worst-case pg176 package capacitance. vout = 0 v, f = 1 mhz 4. all outputs unloaded. all inputs = vcc or gnd, typical icc = 1 ma. icc limit includes ipp and isv during normal operations. 5. vout, vin = vcc or gnd.
act 2 family fpgas revision 8 2-3 package thermal characteristics the device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. the thermal characteristics for ja are shown with two different air flow rates. maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a pq160 package at commercial temperature and still air is as follows: eq 1 power dissipation p = [icc standby + iccactive] * vcc + iol * vol * n + ioh* (vcc ? voh) * m eq 2 where: icc standby is the current flowing when no inputs or outputs are changing iccactive is the current flow ing due to cmos switching. iol and ioh are ttl sink/source currents. vol and voh are ttl level output voltages. n is the number of output s driving ttl loads to vol. m is the number of outputs driving ttl loads to voh. an accurate determination of n and m is problematic al because their values depend on the family type, design details, and on the system i/o. the power can be divided into two components: static and active. table 2-4 ? package thermal characteristics package type * pin count jc ja still air ja 300 ft./min. units ceramic pin grid array 100 5 35 17 c/w 132 5 30 15 c/w 176 8 23 12 c/w ceramic quad flatpack 172 8 25 15 c/w plastic quad flatpack 1 100 13 48 40 c/w 144 15 40 32 c/w 160 15 38 30 c/w plastic leaded chip carrier 84 12 37 28 c/w very thin quad flatpack 100 12 43 35 c/w thin quad flatpack 176 15 32 25 c/w notes: (maximum power in still air) 1. maximum power dissipation values for pqfp pa ckages are 1.9 w (pq100), 2.3 w (pq144), and 2.4 w (pq160). 2. maximum power dissipation for plcc packages is 2.7 w. 3. maximum power dissipation for vqfp packages is 2.3 w. 4. maximum power dissipation for tqfp packages is 3.1 w. max. junction temp. (c) max. ambient temp. (c) ? ja c/w ------------------------------------------------------------------------------------------------------------------------------- -------- 150c 70c ? 33c/w ----------------------------------- - 2.4 w ==
detailed specifications 2-4 revision 8 static power component microsemi fpgas have small static power components t hat result in lower power dissipation than pals or plds. by integrating multiple pals/plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. standby power is calculated in ta b l e 2 - 5 for commercial, worst case conditions. the static power dissipated by ttl loads depends on the number of outputs driving high or low and the dc load current. again, this value is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33 v will generate 42 mw with all outputs driving low, an d 140 mw with all outputs driving high. the actual dissipation will average somewhere between as i/os switch states with time. active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unpr ogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissip ation is the totem-pole current in cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. equivalent capacitance the power dissipated by a cmos circuit can be expressed by eq 3 . power (w) = c eq * vcc 2 * f eq 3 where: c eq is the equivalent capacitance expressed in pf. vcc is the power supply in volts. f is the switching frequency in mhz. equivalent capacitance is calculated by measuring icc active at a specified frequency and voltage for each circuit component of interest. measurements have been made over a range of frequencies at a fixed value of vcc. equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. equi valent capacitance values are shown in table 2-6 . table 2-5 ? standby power calculation icc vcc power 2 ma 5.25 v 10.5 mw table 2-6 ? ceq values for microsemi fpgas item ceq value modules (c eqm ) 5.8 input buffers (c eqi ) 12.9 output buffers (c eqo ) 23.8 routed array clock buffer loads (c eqcr )3.9
act 2 family fpgas revision 8 2-5 to calculate the active power dissipated from the co mplete design, the switch ing frequency of each part of the logic must be known. eq 4 shows a piece-wise linear summation over all components. power =vcc 2 * [(m * c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q1 * c eqcr * f q1 ) routed_clk1 + (r1 * f q1 ) routed_clk1 + 0.5 * (q2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 eq 4 where: m = number of logic modules switching at f m n = number of input buffers switching at f n p = number of output buffers switching at f p q1 = number of clock loads on the first routed array clock q2 = number of clock loads on the second routed array clock r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz table 2-7 ? fixed capacitance values for microsemi fpgas device type r1, routed_clk1 r2, routed_clk2 a1225a 106 106.0 a1240a 134 134.2 a1280a 168 167.8
detailed specifications 2-6 revision 8 determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the following guidelines are meant to represent wors t-case scenarios so that they can be generally used to predict the upper limi ts of power dissipation. these guidelines are given in table 2-8 . table 2-8 ? guidelines for predicting power dissipation data value logic modules (m) 80% of modules inputs switching (n) # inputs/4 outputs switching (p) # output/4 first routed array clock loads (q1) 40% of sequential modules second routed array clock loads (q2) 40% of sequential modules load capacitance (c l ) 35 pf average logic module switching rate (f m )f/10 average input switching rate (f n )f/5 average output switching rate (f p )f/10 average first routed array clock rate (f q1 )f average second routed array clock rate (f q2 )f/2
act 2 family fpgas revision 8 2-7 act 2 timing model 1 notes: 1. values shown for a1240a-2 at worst-case commercial conditions. 2. input module predicted routing delay figure 2-1 ? timing model output delays internal delays input delays t inh = 2.0 ns t insu = 4.0 ns i/o module d q t ingl = 4.7 ns t inyl = 2.6 ns t ird2 = 4.8 ns (2) combinatorial logic module t pd = 3.8 ns sequential logic module i/o module t rd1 = 1.4 ns t dlh = 8.0 ns i/o module array clocks f max = 100 mhz combin- atorial logic included in t sud d q d q t outh = 0.0 ns t outsu = 0.4 ns t glh = 9.0 ns t dlh = 8.0 ns t enhz = 7.1 ns t rd1 = 1.4 ns t co = 3.8 ns t sud = 0.4 ns t hd = 0.0 ns t rd4 = 3.1 ns t rd8 = 4.7 ns predicted routing delays t ckh = 11.8 ns g g fo = 256 t rd2 = 1.7 ns
detailed specifications 2-8 revision 8 parameter measurement figure 2-2 ? output buffer delays figure 2-3 ? ac test loads figure 2-4 ? input buffer delays to ac test loads (shown below) pa d d e tribuff in vcc gnd 50% pad vol voh 1.5 v t dhs, 50% 1.5 v t dhs e vcc gnd 50% pad vol 1.5 v t enzl 50% 10% t enlz e vcc gnd 50% pad gnd voh 1.5 v t enzh 50% 90% t enhz vcc load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 50 pf to the output under test vcc gnd 50 pf to the output under test r to vcc for t plz / t pzl r to gnd for t phz / t pzh r = 1 k
act 2 family fpgas revision 8 2-9 sequential module timing characteristics figure 2-5 ? module delays s a b y s, a or b y gnd vcc 50% t plh y gnd gnd vcc 50% 50% 50% vcc 50% 50% t phl t phl t plh note: d represents all data functions involving a, b, and s for multiplexed flip-flops. figure 2-6 ? flip-flops and latches (positive edge triggered) e d clk clr y d* g, clk q e pre, clr t wclka t wasyn t hd t sud t a t wclki t suena t co t rs t hena
detailed specifications 2-10 revision 8 figure 2-7 ? input buffe r latches figure 2-8 ? output buffer latches g pad pad clk data g clk t inh clkbuf t insu t suext t hext ibdl data d g t outsu t outh pa d obdlhs d g
act 2 family fpgas revision 8 2-11 timing derating factor (t emperature and voltage) table 2-9 ? timing derating factor (temperature and voltage) (commercial mini mum/maximum specification) x industrial military min. max. min. max. 0.69 1.11 0.67 1.23 table 2-10 ? timing derating factor for designs at typical temperature (t j = 25c) and voltage (5.0 v) (commercial maximum specification) x 0.85 table 2-11 ? temperature and voltage derating factors (normalized to worst-case commercial, tj = 4.75 v, 70c) ?55?400 257085125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.13 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 note: this derating factor applies to all routing and propagation delays. figure 2-9 ? junction temperature and voltage derating curves (normalized to worst-case commercial, t j = 4.75 v, 70c) 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 4.504.755.005.255.50 r o t c a f g n i t a r e d voltage (v) 125 ? c 85 ? c 70 ? c 25 ? c 0 ? c ?40 ? c ?55 ? c
detailed specifications 2-12 revision 8 a1225a timing characteristics table 2-12 ? a1225a worst-case commercial conditions, vcc = 4.75 v, t j = 70c logic module propagation delays 1 ?2 speed 3 ?1 speed std. speed units parameter/description min. max. min. max. min. max. t pd1 single module 3.8 4.3 5.0 ns t co sequential clock to q 3.8 4.3 5.0 ns t go latch g to q 3.8 4.3 5.0 ns t rs flip-flop (latch) reset to q 3.8 4.3 5.0 ns predicted routing delays 2 t rd1 fo = 1 routing delay 1.1 1.2 1.4 ns t rd2 fo = 2 routing delay 1.7 1.9 2.2 ns t rd3 fo = 3 routing delay 2.3 2.6 3.0 ns t rd4 fo = 4 routing delay 2.8 3.1 3.7 ns t rd8 fo = 8 routing delay 4.4 4.9 5.8 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.8 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.5 5.0 6.0 ns t wasyn flip-flop (latch) clock asynch ronous pulse width 4.5 5.0 6.0 ns t a flip-flop clock input period 9.4 11.0 13.0 ns t inh input buffer latch hold 0.0 0.0 0.0 ns t insu input buffer latch setup 0.4 0.4 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 ns t outsu output buffer latch setup 0.4 0.4 0.5 ns f max flip-flop (latch) clock frequency 105.0 90.0 75.0 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud ?whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time.
act 2 family fpgas revision 8 2-13 a1225a timing characte ristics (continued) table 2-13 ? a1225a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?2 speed ?1 speed std. speed units parameter/description min. max. min. max. min. max. t inyh pad to y high 2.9 3.3 3.8 ns t inyl pad to y low 2.6 3.0 3.5 ns t ingh g to y high 5.0 5.7 6.6 ns t ingl g to y low 4.7 5.4 6.3 ns input module predicted input routing delays * t ird1 fo = 1 routing delay 4.1 4.6 5.4 ns t ird2 fo = 2 routing delay 4.6 5.2 6.1 ns t ird3 fo = 3 routing delay 5.3 6.0 7.1 ns t ird4 fo = 4 routing delay 5.7 6.4 7.6 ns t ird8 fo = 8 routing delay 7.4 8.3 9.8 ns global clock network t ckh input low to high fo = 32 10.2 11.0 12.8 ns fo = 256 11.8 13.0 15.7 t ckl input high to low fo = 32 10.2 11.0 12.8 ns fo = 256 12.0 13.2 15.9 t pwh minimum pulse width high fo = 32 3.4 4.1 4.5 ns fo = 256 3.8 4.5 5.0 t pwl minimum pulse width low fo = 32 3.4 4.1 4.5 ns fo = 256 3.8 4.5 5.0 t cksw maximum skew fo = 32 0.7 0.7 0.7 ns fo = 256 3.5 3.5 3.5 t suext input latch external setup fo = 32 0.0 0.0 0.0 ns fo = 256 0.0 0.0 0.0 t hext input latch external hold fo = 32 7.0 7.0 7.0 ns fo = 256 11.2 11.2 11.2 t p minimum period fo = 32 7.7 8.3 9.1 ns fo = 256 8.1 8.8 10.0 f max maximum frequency fo = 32 130.0 120.0 110.0 ns fo = 256 125.0 115.0 100.0 note: *these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typica l designs across worst-case operating conditions. post- route timing analysis or simulation is required to determi ne actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
detailed specifications 2-14 revision 8 a1225a timing characte ristics (continued) table 2-14 ? a1225a worst-case commercial conditions, vcc = 4.75 v, t j = 70c ttl output module timing 1 ?2 speed ?1 speed std. speed units parameter/description min. max. min. max. min. max. t dlh data to pad high 8.0 9.0 10.6 ns t dhl data to pad low 10.1 11.4 13.4 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.6 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.3 9.5 11.1 ns t glh g to pad high 8.9 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.07 0.08 0.09 ns/pf d thl delta high to low 0.12 0.13 0.16 ns/pf cmos output module timing 1 t dlh data to pad high 10.1 11.5 13.5 ns t dhl data to pad low 8.4 9.6 11.2 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.6 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.3 9.5 11.1 ns t glh g to pad high 8.9 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.12 0.13 0.16 ns/pf d thl delta high to low 0.09 0.10 0.12 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
act 2 family fpgas revision 8 2-15 a1240a timing characteristics table 2-15 ? a1240a worst-case commercial conditions, vcc = 4.75 v, t j = 70c logic module propagation delays 1 ?2 speed 3 ?1 speed std. speed units parameter/description min. max. min. max. min. max. t pd1 single module 3.8 4.3 5.0 ns t co sequential clock to q 3.8 4.3 5.0 ns t go latch g to q 3.8 4.3 5.0 ns t rs flip-flop (latch) reset to q 3.8 4.3 5.0 ns predicted routing delays 2 t rd1 fo = 1 routing delay 1.4 1.5 1.8 ns t rd2 fo = 2 routing delay 1.7 2.0 2.3 ns t rd3 fo = 3 routing delay 2.3 2.6 3.0 ns t rd4 fo = 4 routing delay 3.1 3.5 4.1 ns t rd8 fo = 8 routing delay 4.7 5.4 6.3 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.8 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 4.5 6.0 6.5 ns t wasyn flip-flop (latch) clock asynch ronous pulse width 4.5 6.0 6.5 ns t a flip-flop clock input period 9.8 12.0 15.0 ns t inh input buffer latch hold 0.0 0.0 0.0 ns t insu input buffer latch setup 0.4 0.4 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 ns t outsu output buffer latch setup 0.4 0.4 0.5 ns f max flip-flop (latch) clock frequency 100.0 80.0 66.0 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud ?whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time.
detailed specifications 2-16 revision 8 a1240a timing characte ristics (continued) table 2-16 ? a1240a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?2 speed ?1 speed std. speed units parameter/description min. max. min. max. min. max. t inyh pad to y high 2.9 3.3 3.8 ns t inyl pad to y low 2.6 3.0 3.5 ns t ingh g to y high 5.0 5.7 6.6 ns t ingl g to y low 4.7 5.4 6.3 ns input module predicted input routing delays * t ird1 fo = 1 routing delay 4.2 4.8 5.6 ns t ird2 fo = 2 routing delay 4.8 5.4 6.4 ns t ird3 fo = 3 routing delay 5.4 6.1 7.2 ns t ird4 fo = 4 routing delay 5.9 6.7 7.9 ns t ird8 fo = 8 routing delay 7.9 8.9 10.5 ns global clock network t ckh input low to high fo = 32 10.2 11.0 12.8 ns fo = 256 11.8 13.0 15.7 t ckl input high to low fo = 32 10.2 11.0 12.8 ns fo = 256 12.0 13.2 15.9 t pwh minimum pulse width high fo = 32 3.8 4.5 5.5 ns fo = 256 4.1 5.0 5.8 t pwl minimum pulse width low fo = 32 3.8 4.5 5.5 ns fo = 256 4.1 5.0 5.8 t cksw maximum skew fo = 32 0.5 0.5 0.5 ns fo = 256 2.5 2.5 2.5 t suext input latch external setup fo = 32 0.0 0.0 0.0 ns fo = 256 0.0 0.0 0.0 t hext input latch external hold fo = 32 7.0 7.0 7.0 ns fo = 256 11.2 11.2 11.2 t p minimum period fo = 32 8.1 9.1 11.1 ns fo = 256 8.8 10.0 11.7 f max maximum frequency fo = 32 125.0 110.0 90.0 ns fo = 256 115.0 100.0 85.0 note: *these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typica l designs across worst-case operating conditions. post- route timing analysis or simulation is required to determi ne actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
act 2 family fpgas revision 8 2-17 a1240a timing characte ristics (continued) table 2-17 ? a1240a worst-case commercial conditions, vcc = 4.75 v, t j = 70c ttl output module timing 1 ?2 speed ?1 speed std. speed units parameter/description min. max. min. max. min. max. t dlh data to pad high 8.0 9.0 10.6 ns t dhl data to pad low 10.1 11.4 13.4 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.7 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.07 0.08 0.09 ns/pf d thl delta high to low 0.12 0.13 0.16 ns/pf cmos output module timing 1 t dlh data to pad high 10.2 11.5 13.5 ns t dhl data to pad low 8.4 9.6 11.2 ns t enzh enable pad z to high 8.9 10.0 11.8 ns t enzl enable pad z to low 11.7 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.2 12.7 14.9 ns d tlh delta low to high 0.12 0.13 0.16 ns/pf d thl delta high to low 0.09 0.10 0.12 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
detailed specifications 2-18 revision 8 a1280a timing characteristics table 2-18 ? a1280a worst-case commercial conditions, vcc = 4.75 v, t j = 70c logic module propagation delays 1 ?2 speed 3 ?1 speed std. speed units parameter/description min. max. min. max. min. max. t pd1 single module 3.8 4.3 5.0 ns t co sequential clock to q 3.8 4.3 5.0 ns t go latch g to q 3.8 4.3 5.0 ns t rs flip-flop (latch) reset to q 3.8 4.3 5.0 ns predicted routing delays 2 t rd1 fo = 1 routing delay 1.7 2.0 2.3 ns t rd2 fo = 2 routing delay 2.5 2.8 3.3 ns t rd3 fo = 3 routing delay 3.0 3.4 4.0 ns t rd4 fo = 4 routing delay 3.7 4.2 4.9 ns t rd8 fo = 8 routing delay 6.7 7.5 8.8 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input setup 0.4 0.4 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.8 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 5.5 6.0 7.0 ns t wasyn flip-flop (latch) clock asynch ronous pulse width 5.5 6.0 7.0 ns t a flip-flop clock input period 11.7 13.3 18.0 ns t inh input buffer latch hold 0.0 0.0 0.0 ns t insu input buffer latch setup 0.4 0.4 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 ns t outsu output buffer latch setup 0.4 0.4 0.5 ns f max flip-flop (latch) clock frequency 85.0 75.0 50.0 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud ?whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtained from the directtime analyzer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external setup/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time.
act 2 family fpgas revision 8 2-19 a1280a timing characte ristics (continued) a1280a timing charac teristics (continued) table 2-19 ? a1280a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?2 speed ?1 speed std. speed units parameter/description min. max. min. max. min. max. t inyh pad to y high 2.9 3.3 3.8 ns t inyl pad to y low 2.7 3.0 3.5 ns t ingh g to y high 5.0 5.7 6.6 ns t ingl g to y low 4.8 5.4 6.3 ns input module predicted input routing delays * t ird1 fo = 1 routing delay 4.6 5.1 6.0 ns t ird2 fo = 2 routing delay 5.2 5.9 6.9 ns t ird3 fo = 3 routing delay 5.6 6.3 7.4 ns t ird4 fo = 4 routing delay 6.5 7.3 8.6 ns t ird8 fo = 8 routing delay 9.4 10.5 12.4 ns global clock network t ckh input low to high fo = 32 10.2 11.0 12.8 ns fo = 256 13.1 14.6 17.2 t ckl input high to low fo = 32 10.2 11.0 12.8 ns fo = 256 13.3 14.9 17.5 t pwh minimum pulse width high fo = 32 5.0 5.5 6.6 ns fo = 256 5.8 6.4 7.6 t pwl minimum pulse width low fo = 32 5.0 5.5 6.6 ns fo = 256 5.8 6.4 7.6 t cksw maximum skew fo = 32 0.5 0.5 0.5 ns fo = 256 2.5 2.5 2.5 t suext input latch external setup fo = 32 0.0 0.0 0.0 ns fo = 256 0.0 0.0 0.0 t hext input latch external hold fo = 32 7.0 7.0 7.0 ns fo = 256 11.2 11.2 11.2 t p minimum period fo = 32 9.6 11.2 13.3 ns fo = 256 10.6 12.6 15.3 f max maximum frequency fo = 32 105.0 90.0 75.0 ns fo = 256 95.0 80.0 65.0 note: *these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typica l designs across worst-case operating conditions. post- route timing analysis or simulation is required to determi ne actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
detailed specifications 2-20 revision 8 table 2-20 ? a1280a worst-case commercial conditions, vcc = 4.75 v, t j = 70c ttl output module timing 1 ?2 speed ?1 speed std. speed units parameter/description min. max. min. max. min. max. t dlh data to pad high 8.1 9.0 10.6 ns t dhl data to pad low 10.2 11.4 13.4 ns t enzh enable pad z to high 9.0 10.0 11.8 ns t enzl enable pad z to low 11.8 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.3 12.7 14.9 ns d tlh delta low to high 0.07 0.08 0.09 ns/pf d thl delta high to low 0.12 0.13 0.16 ns/pf cmos output module timing 1 t dlh data to pad high 10.3 11.5 13.5 ns t dhl data to pad low 8.5 9.6 11.2 ns t enzh enable pad z to high 9.0 10.0 11.8 ns t enzl enable pad z to low 11.8 13.2 15.5 ns t enhz enable pad high to z 7.1 8.0 9.4 ns t enlz enable pad low to z 8.4 9.5 11.1 ns t glh g to pad high 9.0 10.2 11.9 ns t ghl g to pad low 11.3 12.7 14.9 ns d tlh delta low to high 0.12 0.13 0.16 ns/pf d thl delta high to low 0.09 0.10 0.12 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
act 2 family fpgas revision 8 2-21 pin descriptions clka clock a (input) ttl clock input for clock distribution networks. the cl ock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clkb clock b (input) ttl clock input for clock distribution networks. the cl ock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground low supply voltage. i/o input/output (input, output) the i/o pin functions as an input, ou tput, three-state, or bi directional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pi ns are automatically driven low by the als software. mode mode (input) the mode pin controls the use of multifunction pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are active. when the mode pin is low, the pins function as i/os. to provide actionprobe capability, the mode pin should be termi nated to gnd through a 10k resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra probe a (output) the probe a pin is used to output data from an y user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb probe b (output) the probe b pin is used to output data from an y user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when debugging has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdo serial data output (output) serial data output for diagnostic probe. sdo is acti ve when the mode pin is hi gh. this pin functions as an i/o when the mode pin is low. vcc 5.0 v supply voltage high supply voltage.

revision 8 3-1 3 ? package pin assignments pl84 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . 12 13 14 15 16 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 68 69 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 84-pin plcc
package pin assignments 3-2 revision 8 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pl84 pin number a1225a function a1240a function a1280a function 2 clkb, i/o clkb, i/o clkb, i/o 4 prb, i/o prb, i/o prb, i/o 6 gnd gnd gnd 10 dclk, i/o dclk, i/o dclk, i/o 12 mode mode mode 22 vcc vcc vcc 23 vcc vcc vcc 28 gnd gnd gnd 43 vcc vcc vcc 49 gnd gnd gnd 52 sdo sdo sdo 63 gnd gnd gnd 64 vcc vcc vcc 65 vcc vcc vcc 70 gnd gnd gnd 76 sdi, i/o sdi, i/o sdi, i/o 81 pra, i/o pra, i/o pra, i/o 83 clka, i/o clka, i/o clka, i/o 84 vcc vcc vcc
act 2 family fpgas revision 8 3-3 pq100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 100-pin pqfp 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 123456789101112131415161718192021222324252627282930
package pin assignments 3-4 revision 8 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pq100 pin number a1225a function 2 dclk, i/o 4mode 9gnd 16 vcc 17 vcc 22 gnd 34 gnd 40 vcc 46 gnd 52 sdo 57 gnd 64 gnd 65 vcc 66 vcc 67 vcc 72 gnd 79 sdi, i/o 84 gnd 87 pra, i/o 89 clka, i/o 90 vcc 92 clkb, i/o 94 prb, i/o 96 gnd pq100 pin number a1225a function
act 2 family fpgas revision 8 3-5 pq144 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 144 1 144-pin pqfp
package pin assignments 3-6 revision 8 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pq144 pin number a1240a function 2mode 9gnd 10 gnd 11 gnd 18 vcc 19 vcc 20 vcc 21 vcc 28 gnd 29 gnd 30 gnd 44 gnd 45 gnd 46 gnd 54 vcc 55 vcc 56 vcc 64 gnd 65 gnd 71 sdo 79 gnd 80 gnd 81 gnd 88 gnd 89 vcc 90 vcc 91 vcc 92 vcc 93 vcc 100 gnd 101 gnd 102 gnd 110 sdi, i/o 116 gnd 117 gnd 118 gnd 123 pra, i/o 125 clka, i/o 126 vcc 127 vcc 128 vcc 130 clkb, i/o 132 prb, i/o 136 gnd 137 gnd 138 gnd 144 dclk, i/o pq144 pin number a1240a function
act 2 family fpgas revision 8 3-7 pq160 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view of the package 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160-pin pqfp
package pin assignments 3-8 revision 8 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pq160 pin number a1280a function 2 dclk, i/o 6vcc 11 gnd 16 prb, i/o 18 clkb, i/o 20 vcc 21 clka, i/o 23 pra, i/o 30 gnd 35 vcc 38 sdi, i/o 40 gnd 44 gnd 49 gnd 54 vcc 57 vcc 58 vcc 59 gnd 60 vcc 61 gnd 64 gnd 69 gnd 80 gnd 82 sdo 86 vcc 89 gn 98 gnd 99 gnd 109 gnd 114 vcc 120 gnd 125 gnd 130 gnd 135 vcc 138 vcc 139 vcc 140 gnd 145 gnd 150 vcc 155 gnd 159 mode 160 gnd pq160 pin number a1280a function
act 2 family fpgas revision 8 3-9 vq100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100-pin vqfp 75 74 73 72 71 69 70 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 32 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 94 95 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
package pin assignments 3-10 revision 8 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. vq100 pin number a1225a function 2mode 7gnd 14 vcc 15 vcc 20 gnd 32 gnd 38 vcc 44 gnd 50 sdo 55 gnd 62 gnd 63 vcc 64 vcc 65 vcc 70 gnd 77 sdi, i/o 82 gnd 85 pra, i/o 87 clka, i/o 88 vcc 90 clkb, i/o 92 prb, i/o 94 gnd 100 dclk, i/o vq100 pin number a1225a function
act 2 family fpgas revision 8 3-11 tq176 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 140 139 138 137 176-pin tqfp 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 136 135 134 133
package pin assignments 3-12 revision 8 tq176 pin number a1240a function a1280a function 1gnd gnd 2 mode mode 8nc nc 10 nc i/o 11 nc i/o 13 nc vcc 18 gnd gnd 19 nc i/o 20 nc i/o 22 nc i/o 23 gnd gnd 24 nc vcc 25 vcc vcc 26 nc i/o 27 nc i/o 28 vcc vcc 29 nc i/o 33 nc nc 37 nc i/o 38 nc nc 45 gnd gnd 52 nc vcc 54 nc i/o 55 nc i/o 57 nc nc 61 nc i/o 64 nc i/o 66 nc i/o 67 gnd gnd 68 vcc vcc 74 nc i/o 77 nc nc 78 nc i/o 80 nc i/o 82 nc vcc 86 nc i/o 87 sdo sdo 89 gnd gnd 96 nc i/o 97 nc i/o 101 nc nc 103 nc i/o 106 gnd gnd 107 nc i/o 108 nc i/o 109 gnd gnd 110 vcc vcc 111 gnd gnd 112 vcc vcc 113 vcc vcc 114 nc i/o 115 nc i/o 116 nc vcc 121 nc nc 124 nc i/o 125 nc i/o 126 nc nc 133 gnd gnd 135 sdi, i/o sdi, i/o 136 nc i/o 140 nc vcc 143 nc i/o 144 nc i/o 145 nc nc 147 nc i/o 151 nc i/o 152 pra, i/o pra, i/o 154 clka, i/o clka, i/o tq176 pin number a1240a function a1280a function
act 2 family fpgas revision 8 3-13 notes: 1. nc denotes no connection. 2. all unlisted pin num bers are user i/os. 3. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 155 vcc vcc 156 gnd gnd 158 clkb, i/o clkb, i/o 160 prb, i/o prb, i/o 161 nc i/o 165 nc nc 166 nc i/o 168 nc i/o 170 nc vcc 173 nc i/o 175 dclk, i/o dclk, i/o tq176 pin number a1240a function a1280a function
package pin assignments 3-14 revision 8 cq172 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 172-pin cqfp pin #1 index 172 1
act 2 family fpgas revision 8 3-15 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. cq172 pin number a1280a function 1mode 7gnd 12 vcc 17 gnd 22 gnd 23 vcc 24 vcc 27 vcc 32 gnd 37 gnd 50 vcc 55 gnd 65 gnd 66 vcc 75 gnd 80 vcc 85 sdo 98 gnd 103 gnd 106 gnd 107 vcc 108 gnd 109 vcc 110 vcc 113 vcc 118 gnd 123 gnd 131 sdi, i/o 136 vcc 141 gnd 148 pra, i/o 150 clka, i/o 151 vcc 152 gnd 154 clkb, i/o 156 prb, i/o 161 gnd 166 vcc 171 dclk, i/o cq172 pin number a1280a function
package pin assignments 3-16 revision 8 pg100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 1 a 234567891011 b c d e f g h j k l a b c d e f g h j k l 100-pin cpga 1234567891011 orientation pin
act 2 family fpgas revision 8 3-17 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pg100 pin number a1225a function a4 prb, i/o a7 pra, i/o b6 vcc c2 mode c3 dclk, i/o c5 gnd c6 clka, i/o c7 gnd c8 sdi, i/o d6 clkb, i/o d10 gnd e3 gnd e11 vcc f3 vcc f9 vcc f10 vcc f11 gnd g1 vcc g3 gnd g9 gnd j5 gnd j7 gnd j9 sdo k6 vcc pg100 pin number a1225a function
package pin assignments 3-18 revision 8 pg132 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 132-pin cpga a b c d e f g h j k l m n a b c d e f g h j k l m n orientation pin 1 2 3 4 5 6 7 8 9 10111213 1 2 3 4 5 6 7 8 9 10111213
act 2 family fpgas revision 8 3-19 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pg132 pin number a1240a function a1 mode b5 gnd b6 clkb, i/o b7 clka, i/o b8 pra, i/o b9 gnd b12 sdi, i/o c3 dclk, i/o c5 gnd c6 prb, i/o c7 vcc c9 gnd d7 vcc e3 gnd e11 gnd e12 gnd f4 gnd g2 vcc g3 vcc g4 vcc g10 vcc g11 vcc g12 vcc g13 vcc h13 gnd j2 gnd j3 gnd j11 gnd k7 vcc k12 gnd l5 gnd l7 vcc l9 gnd m9 gnd n12 sdo pg132 pin number a1240a function
package pin assignments 3-20 revision 8 pg176 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx 1 a 234567891011 b c d e f g h j k l 176-pin cpga 1234567891011 12 12 13 13 14 14 15 15 m n p r a b c d e f g h j k l m n p r
act 2 family fpgas revision 8 3-21 notes: 1. all unlisted pin num bers are user i/os. 2. mode pin should be terminated to gnd through a 10k re sistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pg176 pin number a1280a function a9 clka, i/o b3 dclk, i/o b8 clkb, i/o b14 sdi, i/o c3 mode c8 gnd c9 pra, i/o d4 gnd d5 vcc d6 gnd d7 prb, i/o d8 vcc d10 gnd d11 vcc d12 gnd e4 gnd e12 gnd f4 vcc f12 gnd g4 gnd g12 vcc h2 vcc h3 vcc h4 gnd h12 gnd h13 vcc h14 vcc j4 vcc j12 gnd j13 gnd j14 vcc k4 gnd k12 gnd l4 gnd m4 gnd m5 vcc m6 gnd m8 gnd m10 gnd m11 vcc m12 gnd n8 vcc p13 sdo pg176 pin number a1280a function

revision 8 4-1 4 ? datasheet information list of changes the following table lists critical changes that were made in each version of the datasheet. revision changes page revision 8 (january 2012) the act 2 datasheet was formatted newly in the style used for current datasheets. the same information is present (other t han noted in the list of changes for this revision) but divided into chapters. n/a package names used in table 1 ? act 2 product family profile and throughout the document were revised to match standards given in package mechanical drawings (sar 27395). i the description for sdo pins had earlier been removed from the datasheet and has now been included again, in the "pin descript ions" section (sar 35819). 2-21 sdo pin numbers had earlier been removed from package pin assignment tables in the datasheet, and have now been restored to the pin tables (sar 35819). 3-2 revision 7 (june 2006) the "ordering information" section was revised to include rohs information. ii revision 6 (december 2000) in the "pg176" package, pin a3 was incorrectly assigned as clka, i/o. a3 is a user i/o. pin a9 is clka, i/o. 3-21
datasheet information 4-2 revision 8 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device is designated as either "product brief," "advance," "pre liminary," or "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the products described in this advance status document may not have completed the microsemi qualification process. products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult the microsemi soc products group terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available at http://www.microsemi.com/s oc/documents/ort_report.pdf . microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local sales office for additional reliability information.

5172104-8/1.12 ? 2012 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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